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P89LPC952/954
8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC
Rev. 04 -- 24 July 2008 Product data sheet
1. General description
The P89LPC952/954 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC952/954 in order to reduce component count, board space, and system cost.
2. Features
2.1 Principal features
I 8 kB/16 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. I 256-byte RAM data memory and a 256-byte auxiliary on-chip RAM. I 8-input multiplexed 10-bit ADC with window comparator that can generate an interrupt for in or out of range results. Two analog comparators with selectable inputs and reference source. I Two 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to become a PWM output) and a 23-bit system timer that can also be used as a RTC. I Two enhanced UARTs with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I2C-bus communication port and SPI communication port. I High-accuracy internal RC oscillator option, with clock doubler option, allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. Fast switching between the internal RC oscillator and any oscillator source provides optimal support of minimal power active mode with fast switching to maximum performance. I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). I 44-pin and 48-pin packages with 40 and 42 I/O pins minimum while using on-chip oscillator and reset options. I Port 5 has high current sourcing/sinking (20 mA) for all Port 5 pins. All other port pins have high sinking capability (20 mA). A maximum limit is specified for the entire chip. I Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values.
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
2.2 Additional features
I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. I Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. I Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application. I In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application. I Low voltage (brownout) detect allows a graceful system shutdown when power fails. May optionally be configured as an interrupt. I Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 A (total power-down with voltage comparators disabled). I On-chip power-on reset allows operation without external reset components. A software reset function is also available. I Programmable external reset pin (P1.5) configuration options: open drain bidirectional reset input/output, reset input with pull-up, push-pull reset output, input-only port. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. I Only power and ground connections are required to operate the P89LPC952/954 when internal reset option is selected. I Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz. I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. I Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. I Port `input pattern match' detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. I Four interrupt priority levels. I Eight keypad interrupt inputs, plus two additional external interrupt inputs. I Schmitt trigger port inputs. I Second data pointer. I Extended temperature range. I Emulation support.
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Product data sheet
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
3. Ordering information
Table 1. Ordering information Package Name P89LPC952FA P89LPC952FBD P89LPC954FA P89LPC954FBD44 P89LPC954FBD48 PLCC44 LQFP44 PLCC44 LQFP44 LQFP48 Description plastic leaded chip carrier; 44 leads plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm plastic leaded chip carrier; 44 leads plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm Version SOT187-2 SOT389-1 SOT187-2 SOT389-1 SOT313-2 Type number
3.1 Ordering options
Table 2. Ordering options Flash memory 8 kB 8 kB 16 kB 16 kB 16 kB Temperature range -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C Frequency 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz Type number P89LPC952FA P89LPC952FBD P89LPC954FA P89LPC954FBD44 P89LPC954FBD48
P89LPC952_954_4
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Product data sheet
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
4. Block diagram
P89LPC952/954
ACCELERATED 2-CLOCK 80C51 CPU
8 kB/16 kB CODE FLASH 256-BYTE DATA RAM 256-BYTE AUXILIARY RAM internal bus
UART0
TXD0 RXD0 TXD1 RXD1 SCL SDA AD00 AD01 AD03 AD05 AD07
UART1
I2C-BUS
P5[7:0]
PORT 5 CONFIGURABLE I/Os PORT 4 CONFIGURABLE I/Os PORT 3 CONFIGURABLE I/Os PORT 2 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os
AD02 ADC0 AD04 AD06 SPICLK MOSI MISO SS
P4[7:0]
P3[1:0] P2[5:0](1) P2[7:0](2) P1[7:0]
SPI
REAL-TIME CLOCK/ SYSTEM TIMER TIMER 0 TIMER 1 T0 T1 CMP2 ANALOG COMPARATORS CIN2A CIN1A CIN2B CMP1 CIN1B
P0[7:0]
KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR DEBUGGER INTERFACE
TRIG TCLK TDI
PROGRAMMABLE OSCILLATOR DIVIDER XTAL1 CRYSTAL OR RESONATOR XTAL2
CPU clock ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
CONFIGURABLE OSCILLATOR
002aab305
(1) 44-pin package. (2) 48-pin package.
Fig 1.
Block diagram
P89LPC952_954_4
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Product data sheet
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
5. Functional diagram
VDD VSS
AD05 AD00 AD01 AD02 AD03
KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 CLKOUT
CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 T1 XTAL2
PORT 0
PORT 1
TXD0 RXD0 T0 INT0 INT1 RST AD04 AD07 AD06 MOSI MISO SS SPICLK
SCL SDA
PORT 3 XTAL1
P89LPC952 P89LPC954
(1) (1)
PORT 2
PORT 5 TRIG TXD1 RXD1 TDI TCLK
002aab358
PORT 4
(1) 48-pin package.
Fig 2.
Functional diagram
P89LPC952_954_4
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Product data sheet
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
6. Pinning information
6.1 Pinning
42 P0.1/CIN2B/KBI1/AD00 41 P0.2/CIN2A/KBI2/AD01 40 P0.3/CIN1B/KBI3/AD02 39 P0.4/CIN1A/KBI4/AD03 38 P0.5/CMPREF/KBI5 37 P0.6/CMP1/KBI6 36 VDD 35 P0.7/T1/KBI7 34 P2.2/MOSI 33 P2.3/MISO 32 P2.4/SS 31 P2.5/SPICLK 30 P4.0 29 P4.1/TRIG P5.3 18 P5.2 19 P5.1 20 P5.0 21 VSS 22 P4.7/TCLK 23 P4.6 24 P4.5/TDI 25 P4.4 26 P4.3/RXD1 27 P4.2/TXD1 28
002aab307
P1.3/INT0/SDA P1.2/T0/SCL P1.1/RXD0
7 8 9
P1.0/TXD0 10 P3.1/XTAL1 11 P3.0/XTAL2/CLKOUT 12 VDD 13 P5.7 14 P5.6 15 P5.5 16 P5.4 17
P89LPC952FA P89LPC954FA
Fig 3.
PLCC44 pin configuration
P89LPC952_954_4
43 P0.0/CMP2/KBI0/AD05
P2.0/AD07 1
44 P2.1/AD06
6
5
4
3
2
P1.7/AD04
P1.4/INT1
P1.5/RST
P1.6
VSS
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
36 P0.1/CIN2B/KBI1/AD00
35 P0.2/CIN2A/KBI2/AD01
P1.3/INT0/SDA P1.2/T0/SCL P1.1/RXD0 P1.0/TXD0 P3.1/XTAL1 P3.0/XTAL2/CLKOUT VDD P5.7 P5.6
1 2 3 4 5 6 7 8 9
34 P0.3/CIN1B/KBI3/AD02 33 P0.4/CIN1A/KBI4/AD03 32 P0.5/CMPREF/KBI5 31 P0.6/CMP1/KBI6 30 VDD 29 P0.7/T1/KBI7 28 P2.2/MOSI 27 P2.3/MISO 26 P2.4/SS 25 P2.5/SPICLK 24 P4.0 23 P4.1/TRIG P4.2/TXD1 22
002aab306
P89LPC952FBD P89LPC954FBD
P5.5 10 P5.4 11 P5.3 12 P5.2 13 P5.1 14 P5.0 15 VSS 16 P4.7/TCLK 17 P4.6 18 P4.5/TDI 19 P4.4 20 P4.3/RXD1 21
Fig 4.
LQFP44 pin configuration
P89LPC952_954_4
37 P0.0/CMP2/KBI0/AD05
41 VSS 40 P1.7/AD04
39 P2.0/AD07
38 P2.1/AD06
44 P1.4/INT1
43 P1.5/RST
42 P1.6
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
39 P0.1/CIN2B/KBI1/AD00
38 P0.2/CIN2A/KBI2/AD01
P1.3/INT0/SDA P1.2/T0/SCL P1.1/RXD0 P1.0/TXD0 P2.7 P3.1/XTAL1 P3.0/XTAL2/CLKOUT VDD P5.7
1 2 3 4 5 6 7 8 9
37 P0.3/CIN1B/KBI3/AD02 36 P0.4/CIN1A/KBI4/AD03 35 P0.5/CMPREF/KBI5 34 P0.6/CMP1/KBI6 33 VREFP 32 VDD 31 P0.7/T1/KBI7 30 P2.2/MOSI 29 P2.3/MISO 28 P2.4/SS 27 P2.5/SPICLK 26 P2.6 25 P4.0 P4.1/TRIG 24
002aad095
P89LPC954FBD48
P5.6 10 P5.5 11 P5.4 12 P5.3 13 P5.2 14 P5.1 15 P5.0 16 VSS 17 P4.7/TCLK 18 P4.6 19 P4.5/TDI 20 P4.4 21 P4.3/RXD1 22 P4.2/TXD1 23
Fig 5.
LQFP48 pin configuration
P89LPC952_954_4
40 P0.0/CMP2/KBI0/AD05
43 P1.7/AD04
42 P2.0/AD07
41 P2.1/AD06
48 P1.4/INT1
47 P1.5/RST
44 VREFN
46 P1.6
45 VSS
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
6.2 Pin description
Table 3. Symbol P0.0 to P0.7 Pin description Pin LQFP48 PLCC44 LQFP44 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.13.1 "Port configurations" and Table 11 "Static characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: P0.0/CMP2/ KBI0/AD05 40 43 37 I/O O I I P0.1/CIN2B/ KBI1/AD00 39 42 36 I/O I I I P0.2/CIN2A/ KBI2/AD01 38 41 35 I/O I I I P0.3/CIN1B/ KBI3/AD02 37 40 34 I/O I I I P0.4/CIN1A/ KBI4/AD03 36 39 33 I/O I I I P0.5/CMPREF/ 35 KBI5 38 32 I/O I I P0.0 -- Port 0 bit 0. CMP2 -- Comparator 2 output. KBI0 -- Keyboard input 0. AD05 -- ADC0 channel 5 analog input. P0.1 -- Port 0 bit 1. CIN2B -- Comparator 2 positive input B. KBI1 -- Keyboard input 1. AD00 -- ADC0 channel 0 analog input. P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input A. KBI2 -- Keyboard input 2. AD01 -- ADC0 channel 1 analog input. P0.3 -- Port 0 bit 3. CIN1B -- Comparator 1 positive input B. KBI3 -- Keyboard input 3. AD02 -- ADC0 channel 2 analog input. P0.4 -- Port 0 bit 4. CIN1A -- Comparator 1 positive input A. KBI4 -- Keyboard input 4. AD03 -- ADC0 channel 3 analog input. P0.5 -- Port 0 bit 5. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. Type Description
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
Table 3. Symbol
Pin description ...continued Pin LQFP48 PLCC44 37 LQFP44 31 I/O O I 31 35 29 I/O I/O I P0.6 -- Port 0 bit 6. CMP1 -- Comparator 1 output. KBI6 -- Keyboard input 6. P0.7 -- Port 0 bit 7. T1 -- Timer/counter 1 external count input or overflow output. KBI7 -- Keyboard input 7. 34 Type Description
P0.6/CMP1/ KBI6
P0.7/T1/KBI7
P1.0 to P1.7
I/O, I Port 1: Port 1 is an 8-bit I/O port with a user-configurable [1] output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 7.13.1 "Port configurations" and Table 11 "Static characteristics" for details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:
P1.0/TXD0 P1.1/RXD0 P1.2/T0/SCL
4 3 2
10 9 8
4 3 2
I/O O I/O I I/O I/O I/O
P1.0 -- Port 1 bit 0. TXD0 -- Transmitter output for serial port 0. P1.1 -- Port 1 bit 1. RXD0 -- Receiver input for serial port 0. P1.2 -- Port 1 bit 2 (open-drain when used as output). T0 -- Timer/counter 0 external count input or overflow output (open-drain when used as output). SCL -- I2C-bus serial clock input/output. P1.3 -- Port 1 bit 3 (open-drain when used as output). INT0 -- External interrupt 0 input. SDA -- I2C-bus serial data input/output. P1.4 -- Port 1 bit 4. INT1 -- External interrupt 1 input.
P1.3/INT0/SDA 1
7
1
I/O I I/O
P1.4/INT1
48
6
44
I/O I
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
Table 3. Symbol P1.5/RST
Pin description ...continued Pin LQFP48 47 PLCC44 5 LQFP44 43 I I P1.5 -- Port 1 bit 5 (input only). RST -- External Reset input during power-on or maybe a reset input/output if selected via UCFG1 and UCFG2. When functioning as a reset input or input/output, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. When functioning as a reset output or input/output an internal reset source will drive this pin LOW. Also used during a power-on sequence to force ISP mode. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. P1.6 -- Port 1 bit 6. P1.7 -- Port 1 bit 7. AD04 -- ADC0 channel 4 analog input. Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.13.1 "Port configurations" and Table 11 "Static characteristics" for details. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below: Type Description
P1.6 P1.7/AD04 P2.0 to P2.5
46 43
4 2
42 40
I/O I/O I I/O
P2.0/AD07 P2.1/AD06 P2.2/MOSI
42 41 30
1 44 34
39 38 28
I/O I I/O I I/O I/O
P2.0 -- Port 2 bit 0. AD07 -- ADC0 channel 7 analog input. P2.1 -- Port 2 bit 1. AD06 -- ADC0 channel 6 analog input. P2.2 -- Port 2 bit 2. MOSI -- SPI master out slave in. When configured as master, this pin is output; when configured as slave, this pin is input. P2.3 -- Port 2 bit 3. MISO -- When configured as master, this pin is input, when configured as slave, this pin is output. P2.4 -- Port 2 bit 4. SS -- SPI Slave select.
P2.3/MISO
29
33
27
I/O I/O
P2.4/SS
28
32
26
I/O I/O
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
Table 3. Symbol
Pin description ...continued Pin LQFP48 PLCC44 31 LQFP44 25 I/O I/O P2.5 -- Port 2 bit 5. SPICLK -- SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input. P2.6 -- Port 2 bit 6. P2.7 -- Port 2 bit 7. Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.13.1 "Port configurations" and Table 11 "Static characteristics" for details. All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below: 27 Type Description
P2.5/SPICLK
P2.6 P2.7 P3.0 to P3.1
26 5
-
-
I/O I/O I/O
P3.0/XTAL2/ CLKOUT
7
12
6
I/O O O
P3.0 -- Port 3 bit 0. XTAL2 -- Output from the oscillator amplifier (when a crystal oscillator option is selected via the flash configuration. CLKOUT -- CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the RTC/system timer. P3.1 -- Port 3 bit 1. XTAL1 -- Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the RTC/system timer. Port 4: Port 4 is an 8-bit I/O port with a user-configurable output type. During reset Port 4 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 4 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.13.1 "Port configurations" and Table 11 "Static characteristics" for details. All pins have Schmitt triggered inputs. Port 4 also provides various special functions as described below:
P3.1/XTAL1
6
11
5
I/O I
P4.0 to P4.7
I/O
P4.0 P4.1/TRIG P4.2/TXD1 P4.3/RXD1
25 24 23 22
30 29 28 27
24 23 22 21
I/O I/O O I/O O I/O I
P4.0 -- Port 4 bit 0. P4.1 -- Port 4 bit 1. TRIG -- Debugger trigger output. P4.2 -- Port 4 bit 2. TXD1 -- Transmitter output for serial port 1. P4.3 -- Port 4 bit 3. RXD1 -- Receiver input for serial port 1.
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P89LPC952_954_4
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
Table 3. Symbol P4.4 P4.5/TDI P4.6 P4.7/TCLK
Pin description ...continued Pin LQFP48 21 20 19 18 PLCC44 26 25 24 23 LQFP44 20 19 18 17 I/O I/O I/O I/O I/O I I/O P4.4 -- Port 4 bit 4. P4.5 -- Port 4 bit 5. TDI -- Serial data input/output for debugger interface. P4.6 -- Port 4 bit 6. P4.7 -- Port 4 bit 7. TCLK -- Serial clock input for debugger interface. Port 5: Port 5 is an 8-bit I/O port with a user-configurable output type. During reset Port 5 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 5 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.13.1 "Port configurations" and Table 11 "Static characteristics" for details. All pins have Schmitt triggered inputs. Port 5 also provides various special functions as described below: Type Description
P5.0 to P5.7
P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 VSS VREFN VDD VREFP
[1]
16 15 14 13 12 11 10 9 17, 45 44 8, 32 33
21 20 19 18 17 16 15 14 3, 22 13, 36 -
15 14 13 12 11 10 9 8 16, 41 7, 30 -
I/O I/O I/O I/O I/O I/O I/O I/O I I
P5.0 -- Port 5 bit 0. High current source. P5.1 -- Port 5 bit 1. High current source. P5.2 -- Port 5 bit 2. High current source. P5.3 -- Port 5 bit 3. High current source. P5.4 -- Port 5 bit 4. High current source. P5.5 -- Port 5 bit 5. High current source. P5.6 -- Port 5 bit 6. High current source. P5.7 -- Port 5 bit 7. High current source. Ground: 0 V reference. negative ADC reference voltage Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. positive ADC reference voltage
Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.
P89LPC952_954_4
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
7. Functional description
Remark: Please refer to the P89LPC952/954 User's Manual for a more detailed functional description.
7.1 Special function registers
Remark: SFR accesses are restricted in the following ways:
* User must not attempt to access any SFR locations not defined. * Accesses to any defined SFR locations must be strictly for the functions for the SFRs. * SFR bits labeled `-', `0' or `1' can only be written and read as follows:
- `-' Unless otherwise specified, must be written with `0', but can return any value when read (even if it was written with `0'). It is a reserved bit and may be used in future derivatives. - `0' must be written with `0', and will return a `0' when read. - `1' must be written with `1', and will return a `1' when read.
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Product data sheet Rev. 04 -- 24 July 2008
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NXP Semiconductors
Table 4. Name
Special function registers Description SFR Bit functions and addresses addr. MSB E7 ENBI0 ADI07 BNDI0 CLK2 CLKLP E6 ENADCI0 ADI06 BURST0 CLK1 EBRR E5 TMM0 ADI05 SCC0 CLK0 ENT1 E4 EDGE0 ADI04 SCAN0 ENT0 E3 ADCI0 ADI03 SRST E2 ENADC0 ADI02 0 E1 ADCS01 ADI01 E0H 97H A3H C0H A1H A2H ADCS00 ADI00 DPS Reset value LSB E0 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 00x0 Hex Binary
Bit address ACC[1] AD0CON AD0INS AD0MODA AD0MODB AUXR1 Accumulator ADC0 control register ADC0 input select ADC0 mode register A ADC0 mode register B Auxiliary function register B register Baud rate generator 0 rate low Baud rate generator 0 rate high
Bit address B[1] BRGR0_0 F0H BEH
F7
F6
F5
F4
F3
F2
F1
F0 00 00 0000 0000 0000 0000
BRGR1_0
BFH
00
0000 0000
BRGCON_0 Baud rate generator 0 control CMP1 CMP2 DIVM Comparator 1 control register Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes)
BDH
-
-
-
-
-
-
SBRGS_0
BRGEN_0 00[3]
8-bit microcontroller with 10-bit ADC
xxxx xx00
P89LPC952/954
ACH ADH 95H
-
-
CE1 CE2
CP1 CP2
CN1 CN2
OE1 OE2
CO1 CO2
CMF1 CMF2
00[2] 00[2] 00
xx00 0000 xx00 0000 0000 0000
DPTR
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Table 4. Name DPH DPL FMADRH FMADRL FMCON Special function registers ...continued Description Data pointer high Data pointer low Program flash address high Program flash address low Program flash control (Read) Program flash control (Write) FMDATA I2ADR Program flash data I2C-bus slave address register I2C-bus control register I2C-bus data register Serial clock generator/SCL duty cycle register high Serial clock generator/SCL duty cycle register low I2C-bus status register
Rev. 04 -- 24 July 2008
(c) NXP B.V. 2008. All rights reserved.
Product data sheet 16 of 69
P89LPC952_954_4
NXP Semiconductors
SFR Bit functions and addresses addr. MSB 83H 82H E7H E6H E4H E4H E5H DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 BUSY FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 HVA FMCMD.3 HVE FMCMD.2 SV FMCMD.1
Reset value LSB Hex 00 00 00 00 OI FMCMD.0 00 GC 00 0000 0000 0000 0000 70 Binary 0000 0000 0000 0000 0000 0000 0000 0000 0111 0000
Bit address I2CON[1] I2DAT I2SCLH D8H DAH
DF -
DE I2EN
DD STA
DC STO
DB SI
DA AA
D9 -
D8 CRSEL 00 x000 00x0
8-bit microcontroller with 10-bit ADC
DDH
00
0000 0000
P89LPC952/954
I2SCLL
DCH
00
0000 0000
I2STAT
D9H
STA.4
STA.3
STA.2
STA.1
STA.0
0
0
0
F8
1111 1000
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Table 4. Name Special function registers ...continued Description SFR Bit functions and addresses addr. MSB AF EA EF BF FF AE EWDRT EE EST BE PWDRT PWDRTH FE PST PSTH AD EBO ED BD PBO PBOH FD AC ES/ESR EC BC PS/PSR PSH/ PSRH FC AB ET1 EB ESPI EST1 BB PT1 PT1H FB PSPI PSPIH PEST1 PEST1H AA EX1 EA EC ES1/ESR1 BA PX1 PX1H FA PC PCH PES1/ PESR1 PES1H/ PESR1H A9 ET0 E9 EKBI EADC B9 PT0 PT0H F9 PKBI PKBIH PADC PADCH PATN _SEL A8H Bit address IEN1[1] IEN2 Interrupt enable 1 Interrupt enable 2 Interrupt priority 0 Interrupt priority 0 high Interrupt priority 1 Interrupt priority 1 high Interrupt priority 2 Interrupt priority 2 high Keypad control register Keypad interrupt mask register Keypad pattern register Port 0 E8H D5H Bit address IP0[1] IP0H
Rev. 04 -- 24 July 2008
(c) NXP B.V. 2008. All rights reserved.
Product data sheet 17 of 69
P89LPC952_954_4
NXP Semiconductors
Reset value LSB A8 EX0 E8 EI2C B8 PX0 PX0H F8 PI2C PI2CH KBIF 00[2] 00[2] 00[2] 00[2] 00[2] 00 00x0 0000 00x0 0000 00x0 0000 00x0 0000 00[2] 00[2] x000 0000 x000 0000 00[2] 00[2] 00x0 0000 00x0 0000 00 0000 0000 Hex Binary
Bit address IEN0[1] Interrupt enable 0
B8H B7H
Bit address IP1[1] IP1H IP2 IP2H KBCON KBMASK F8H F7H D6H D7H 94H 86H
8-bit microcontroller with 10-bit ADC
xxxx xx00 0000 0000
P89LPC952/954
KBPATN
93H 87 T1/KB7 97 86 CMP1 /KB6 96 85 CMPREF /KB5 95 RST 84 CIN1A /KB4 94 INT1 83 CIN1B /KB3 93 INT0/SDA 82 CIN2A /KB2 92 T0/SCL 81 CIN2B /KB1 91 RXD0 80 CMP2 /KB0 90 TXD0
FF
1111 1111
Bit address P0[1] 80H Bit address P1[1] Port 1 90H
[2]
[2]
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Table 4. Name Special function registers ...continued Description SFR Bit functions and addresses addr. MSB 97 B7 T3 (P0M1.7) (P0M2.7) (P1M1.7) (P1M2.7) (P2M1.7) (P2M2.7) SMOD1 RTCPD D7 CY 96 B6 TMS (P0M1.6) (P0M2.6) (P1M1.6) (P1M2.6) (P2M1.6) (P2M2.6) SMOD0 D6 AC 95 SPICLK B5 (P0M1.5) (P0M2.5) (P2M1.5) (P2M2.5) BOPD VCPD D5 F0 PT0AD.5 BOF 94 SS B4 (P0M1.4) (P0M2.4) (P1M1.4) (P1M2.4) (P2M1.4) (P2M2.4) BOI ADPD D4 RS1 PT0AD.4 POF 93 MISO B3 RXD1 (P0M1.3) (P0M2.3) (P1M1.3) (P1M2.3) (P2M1.3) (P2M2.3) GF1 I2PD D3 RS0 PT0AD.3 R_BK 92 MOSI B2 TXD1 (P0M1.2) (P0M2.2) (P1M1.2) (P1M2.2) (P2M1.2) (P2M2.2) GF0 SPPD D2 OV PT0AD.2 R_WD 91 B1 XTAL1 TRIG (P0M1.1) (P0M2.1) (P1M1.1) (P1M2.1) (P2M1.1) (P2M2.1) (P3M1.1) (P3M2.1) PMOD1 SPD D1 F1 PT0AD.1 R_SF A0H Bit address P3[1] P4 P5 P0M1 P0M2 P1M1
Rev. 04 -- 24 July 2008
(c) NXP B.V. 2008. All rights reserved.
Product data sheet 18 of 69
P89LPC952_954_4
NXP Semiconductors
Reset value LSB 90 B0 XTAL2 T3EX (P0M1.0) (P0M2.0) (P1M1.0) (P1M2.0) (P2M1.0) (P2M2.0) (P3M1.0) (P3M2.0) PMOD0 D0 P R_EX 00 00
[4] [2] [2] [2] [2]
Hex
Binary
Bit address P2[1] Port 2 Port 3 Port 4 Port 5 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Port 2 output mode 1 Port 2 output mode 2 Port 3 output mode 1 Port 3 output mode 2 Power control register Power control register A Program status word Port 0 digital input disable Reset source register
B0H B3H B4H 84H 85H 91H 92H A4H A5H B1H B2H 87H B5H
FF[2] 00[2] D3[2] 00[2] FF[2] 00[2] 03[2] 00[2] 00 00[2]
1111 1111 0000 0000 11x1 xx11 00x0 xx00 1111 1111 0000 0000 xxxx xx11 xxxx xx00 0000 0000 0000 0000
P1M2 P2M1 P2M2 P3M1 P3M2 PCON PCONA
8-bit microcontroller with 10-bit ADC
P89LPC952/954
Bit address PSW[1] PT0AD RSTSRC D0H F6H DFH
0000 0000 xx00 000x
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Table 4. Name RTCCON RTCH RTCL S0ADDR Special function registers ...continued Description RTC control RTC register high RTC register low Serial port address register Serial port address enable Serial Port data buffer register Serial port control Serial port extended status register Stack pointer SPI control register SPI status register SPI data register Serial port 1 control Serial port 1 extended status register Timer 0 and 1 auxiliary mode SFR Bit functions and addresses addr. MSB D1H D2H D3H A9H RTCF RTCS1 RTCS0 ERTC Reset value LSB RTCEN Hex 60[2][7] 00[7] 00[7] 00 Binary 011x xx00 0000 0000 0000 0000 0000 0000
Product data sheet Rev. 04 -- 24 July 2008
(c) NXP B.V. 2008. All rights reserved. P89LPC952_954_4
NXP Semiconductors
S0ADEN
B9H
00
0000 0000
S0BUF
99H
xx
xxxx xxxx
Bit address S0CON[1] S0STAT 98H BAH
9F SM0_0/FE _0 DBMOD_0
9E SM1_00 INTLO_0
9D SM2_0 CIDIS_0
9C REN_0 DBISEL_0
9B TB8_0 FE_0
9A RB8_0 BR_0
99 TI_0 OE_0
98 RI_0 STINT_0 00 00 0000 0000 0000 0000
SP SPCTL SPSTAT SPDAT S1CON S1STAT
81H E2H E1H E3H B6H D4H SM0_1/FE _1 DBMOD_1 SM1_1 INTLO_1 SM2_1 CIDIS_1 REN_1 DBISEL_1 TB8_1 FE_1 RB8_1 BR_1 TI_1 OE_1 RI_1 STINT_1 SSIG SPIF SPEN WCOL DORD MSTR CPOL CPHA SPR1 SPR0 -
07 04 00 00 00 00
0000 0111 0000 0100 00xx xxxx 0000 0000 0000 0000 0000 0000
8-bit microcontroller with 10-bit ADC
P89LPC952/954
TAMOD
8FH
-
-
-
T1M2
-
-
-
T0M2
00
xxx0 xxx0
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Table 4. Name Special function registers ...continued Description SFR Bit functions and addresses addr. MSB 8F TF1 8E TR1 8D TF0 8C TR0 8B IE1 8A IT1 89 IE0 88H 8CH 8DH 8AH 8BH 89H 96H T1GATE RCCLK T1C/T ENCLK T1M1 TRIM.5 T1M0 TRIM.4 T0GATE TRIM.3 T0C/T TRIM.2 T0M1 TRIM.1 T0M0 TRIM.0 Reset value LSB 88 IT0 00 00 00 00 00 00
[6] [7]
Product data sheet Rev. 04 -- 24 July 2008 20 of 69
P89LPC952_954_4 (c) NXP B.V. 2008. All rights reserved.
NXP Semiconductors
Hex
Binary 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Bit address TCON[1] TH0 TH1 TL0 TL1 TMOD TRIM Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2
WDCON WDL WFEED1 WFEED2
A7H C1H C2H C3H
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
[5] [7]
FF
1111 1111
[1] [2] [3] [4] [5] [6] [7]
Indicates SFRs that are bit addressable.
8-bit microcontroller with 10-bit ADC
All ports are in input only (high-impedance) state after power-up. BRGR1_0 and BRGR0_0 must only be written if BRGEN_0 in BRGCON_0 SFR is logic 0. If any are written while BRGEN_0 = 1, the result is unpredictable. The RSTSRC register reflects the cause of the P89LPC952/954 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset source that affects these SFRs is power-on reset.
P89LPC952/954
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Product data sheet Rev. 04 -- 24 July 2008
(c) NXP B.V. 2008. All rights reserved. P89LPC952_954_4
NXP Semiconductors
Table 5. Name
Extended special function registers Description ADC0 high_boundary register, left (MSB) ADC0 low_boundary register (MSB) ADC0 data register 0, right (LSB) ADC0 data register 0, left (MSB) SFR addr. FFEFH FFEEH FFFEH FFFFH AD0DAT0[7:0] AD0DAT0[9:2] AD0DAT1[7:0] AD0DAT1[9:2] AD0DAT2[7:0] AD0DAT2[9:2] AD0DAT3[7:0] AD0DAT3[9:2] AD0DAT4[7:0] AD0DAT4[9:2] AD0DAT5[7:0] AD0DAT5[9:2] AD0DAT6[7:0] AD0DAT6[9:2] AD0DAT7[7:0] Bit functions and addresses MSB LSB Reset value Hex FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Binary 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
ADC0HBND ADC0LBND AD0DAT0R AD0DAT0L AD0DAT1R AD0DAT1L AD0DAT2R AD0DAT2L AD0DAT3R AD0DAT3L AD0DAT4R AD0DAT4L AD0DAT5R AD0DAT5L AD0DAT6R AD0DAT6L AD0DAT7R
ADC0 data register 1, right FFFCH (LSB) ADC0 data register 1, left (MSB) ADC0 data register 2, right (LSB) ADC0 data register 2, left (MSB) ADC0 data register 3, right (LSB) ADC0 data register 3, left (MSB) ADC0 data register 4, right (LSB) ADC0 data register 4, left (MSB) ADC0 data register 5, right (LSB) ADC0 data register 5, left (MSB) ADC0 data register 6, right (LSB) ADC0 data register 6, left (MSB) ADC0 data register 7, right (LSB) FFFDH FFFAH FFFBH FFF8H FFF9H FFF6H FFF7H FFF4H FFF5H FFF2H FFF3H FFF0H
8-bit microcontroller with 10-bit ADC
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
P89LPC952/954
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Table 5. Name AD0DAT7L BNDSTA0 BRGCON_1 BRG0_1 BRG1_1 FREEZE P4M1
Rev. 04 -- 24 July 2008
(c) NXP B.V. 2008. All rights reserved.
Extended special function registers ...continued Description ADC0 data register 7, left (MSB) ADC0 boundary status register Baud rate generator 1 control SFR addr. FFF1H FFEDH FFB3H SBRGS_1 BRGEN_1 00[2] xxxx xx00 Bit functions and addresses MSB AD0DAT7[9:2] LSB Reset value Hex Binary
Product data sheet 22 of 69
P89LPC952_954_4
NXP Semiconductors
Baud rate generator 1 rate FFB4H low Baud rate generator 1 rate FFB5H high Peripheral clock freeze Port 4 output mode 1 Port 4 output mode 2 Port 5 output mode 1 Port 5 output mode 3 Serial port 1 address register Serial port 1 address enable Serial port 1 data buffer register FFD0H RTC_F CCU_F WDT_F T1_F (P4M1.1) (P4M2.1) (P5M1.1) (P5M2.1) T0_F (P4M1.0) (P4M2.0) (P5M1.0) 00 FF[1] 00[1] FF[1] 00 00 xx xxx0 0000 1111 1111 0000 0000 1111 1111 0000 0000 0000 0000 xxxx xxxx FFB8H (P4M1.7) (P4M1.6) (P4M1.5) (P4M1.4) (P4M1.3) (P4M1.2) FFB9H (P4M2.7) (P4M2.6) (P4M2.5) (P4M2.4) (P4M2.3) (P4M2.2) FFBAH (P5M1.7) (P5M1.6) (P5M1.5) (P5M1.4) (P5M1.3) (P5M1.2) FFBBH (P5M2.7) (P5M2.6) (P5M2.5) (P5M2.4) (P5M2.3) (P5M2.2) FFB2H FFB1H FFB0H
P4M2 P5M1 P5M2 S1ADDR S1ADEN S1BUF
(P5M2.0) 00[1] 0000 0000
8-bit microcontroller with 10-bit ADC
[1] [2]
Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are used to access these extended SFRs. BRGR1_1 and BRGR0_1 must only be written if BRGEN_1 in BRGCON_1 SFR is logic 0. If any are written while BRGEN_1 = 1, the result is unpredictable.
P89LPC952/954
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.2 Enhanced CPU
The P89LPC952/954 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.
7.3 Clocks
7.3.1 Clock definitions
The P89LPC952/954 device has several internal clocks as defined below: OSCCLK -- Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see Figure 6) and can also be optionally divided to a slower frequency (see Section 7.8 "CCLK modification: DIVM register"). Note: fosc is defined as the OSCCLK frequency. CCLK -- CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK -- The internal 7.373 MHz RC oscillator output. The clock doubler option, when enabled, provides an output frequency of 14.746 MHz. PCLK -- Clock for the various peripheral devices and is CCLK2.
7.3.2 CPU clock (OSCCLK)
The P89LPC952/954 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.
7.3.3 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.
7.3.4 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.
7.3.5 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration. When using a clock frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using a clock frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device
P89LPC952_954_4
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Product data sheet
Rev. 04 -- 24 July 2008
23 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
in reset when VDD falls below the minimum specified operating voltage. These requirements for clock frequencies above 12 MHz do not apply when using the internal RC oscillator in clock doubler mode.
7.3.6 Clock output
The P89LPC952/954 supports a user-selectable clock output function on the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on XTAL1) and if the RTC is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC952/954. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is 12 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.
7.4 On-chip RC oscillator option
The P89LPC952/954 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz 1 % at room temperature. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. When the clock doubler option is enabled (UCFG1.3 = 1), the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower. The requirements in Section 7.3.5 "High speed oscillator option" for configuring P1.5 as an external reset input and using an external reset circuit when the clock frequency is greater than 12 MHz do not apply when using the internal RC oscillator's clock doubler option.
7.5 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.
7.6 External clock input option
In this configuration, the processor clock is derived from an external source driving the P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be used as a standard port pin or a clock output. When using an external clock input frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an external clock input frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. These requirements for clock frequencies above 12 MHz do not apply when using the internal RC oscillator in clock doubler mode.
P89LPC952_954_4 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 24 July 2008
24 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
XTAL1 XTAL2
HIGH FREQUENCY MEDIUM FREQUENCY LOW FREQUENCY
RTC
ADC0 RCCLK OSCCLK RC OSCILLATOR WITH CLOCK DOUBLER RCCLK /2 PCLK WDT DIVM CCLK CPU
(7.3728 MHz/14.7456 MHz 1 %) WATCHDOG OSCILLATOR (400 kHz +30 % -20 %) TIMER 0 AND TIMER 1
PCLK
I2C-BUS
SPI
UARTS
002aab409
Fig 6.
Block diagram of oscillator control
7.7 CCLK wake-up delay
The P89LPC952/954 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus 60 s to 100 s. If the clock source is either the internal RC oscillator, watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60 s to 100 s.
7.8 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.
7.9 Low power select
The P89LPC952/954 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to `1' to lower the power consumption further. On any reset, CLKLP is `0' allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
P89LPC952_954_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 24 July 2008
25 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.10 Memory organization
The various P89LPC952/954 memory spaces are as follows:
* DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.
* IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.
* SFR
Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.
* XDATA
`External' Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC952/954 has 256 bytes of on-chip XDATA memory, plus extended SFRs located in XDATA.
* CODE
64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC952/954 has 8 kB/16 kB of on-chip Code memory.
7.11 Data RAM arrangement
The 768 bytes of on-chip RAM are organized as shown in Table 6.
Table 6. Type DATA IDATA XDATA On-chip data memory usages Data RAM Memory that can be addressed directly and indirectly Memory that can be addressed indirectly Auxiliary (`External Data') on-chip memory that is accessed using the MOVX instructions Size (bytes) 128 256 256
7.12 Interrupts
The P89LPC952/954 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC952/954 supports 17 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port 0 TX, serial port 0 RX, combined serial port 0 RX/TX, serial port 1 TX, serial port 1 RX, combined serial port 1 RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, SPI, and ADC completion. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0, IEN1 or IEN2. The IEN0 register also contains a global disable bit, EA, which disables all interrupts.
P89LPC952_954_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 24 July 2008
26 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, IP1H, IP2, and IP2H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.
7.12.1 External interrupt inputs
The P89LPC952/954 has two external interrupt inputs as well as the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers. These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in Register TCON. In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request. If an external interrupt is enabled when the P89LPC952/954 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 7.15 "Power reduction modes" for details.
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IE0 EX0 IE1 EX1 BOF EBO RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF2 CMF1 EC EA (IE0.7) TF0 ET0 TF1 ET1 TI_0 and RI_0/RI_0 ES/ESR TI_0 EST SI EI2C SPIF ESPI TI_1 and RI_1/RI_1 ES1/ESR1 TI_1 EST1 interrupt to CPU
wake-up (if in power-down)
ENADCI0 ADCI0 ENBI0 BNDI0 EADC
002aab408
Fig 7.
Interrupt sources, interrupt enables, and power-down wake-up sources
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7.13 I/O ports
The P89LPC952/954 has six I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5. Ports 0, 1, 2, 4, and 5 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock and reset options and package chosen, as shown in Table 7.
Table 7. Number of I/O pins available Reset option No external reset (except during power-up) External RST pin supported No external reset (except during power-up) External RST pin supported[1] Number of I/O pins Number of I/O pins (48-pin package) (44-pin package) 42 41 41 40 40 39 40 39 39 38 38 37
Clock source On-chip oscillator or watchdog oscillator External clock input
Low/medium/high speed oscillator No external reset (except during power-up) (external crystal or resonator) External RST pin supported[1]
[1] Required for operation above 12 MHz.
7.13.1 Port configurations
All but three I/O port pins on the P89LPC952/954 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. 1. P1.5/RST can only be an input and cannot be configured. 2. P1.2/T0/SCL and P1.3/INT0/SDA may only be configured to be either input-only or open-drain. 7.13.1.1 Quasi-bidirectional output configuration Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. The P89LPC952/954 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged. A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit. 7.13.1.2 Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD.
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An open-drain port pin has a Schmitt triggered input that also has a glitch suppression circuit. 7.13.1.3 Input-only configuration The input-only port configuration has no output drivers. It is a Schmitt triggered input that also has a glitch suppression circuit. 7.13.1.4 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt triggered input that also has a glitch suppression circuit.
7.13.2 Port 0 analog functions
The P89LPC952/954 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-Only (high-impedance) mode. Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5. On any reset, PT0AD[1:5] defaults to `0's to enable digital functions.
7.13.3 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices.
* After power-up, all I/O pins except P1.5, may be configured by software. * Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or
open-drain. Every output on the P89LPC952/954 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 11 for detailed specifications. All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.
7.14 Power monitoring functions
The P89LPC952/954 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on detect and brownout detect.
7.14.1 Brownout detection
The brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a brownout detection to cause a processor reset, however it may alternatively be configured to generate an interrupt.
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Brownout detection may be enabled or disabled in software. If brownout detection is enabled the brownout condition occurs when VDD falls below the brownout trip voltage, Vbo (see Table 11 "Static characteristics"), and is negated when VDD rises above Vbo. If the P89LPC952/954 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating. For correct activation of brownout detect, the VDD rise and fall times must be observed. Please see Table 11 "Static characteristics" for specifications.
7.14.2 Power-on detection
The Power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software.
7.15 Power reduction modes
The P89LPC952/954 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode.
7.15.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.
7.15.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC952/954 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the data retention supply voltage VDDR. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VDDR, therefore it is highly recommended to wake-up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited. Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: Brownout detect, watchdog timer, comparators (note that comparators can be powered down separately), and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled.
7.15.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the RTC running during power-down.
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7.16 Reset
The P1.5/RST pin can function as either a digital input (P1.5), an active-LOW reset input with an internal pull-up, a bidirectional reset input/output (open drain output with an internal pull-up), or as push-pull reset output. These modes are selected by the RPE (Reset Pin Enable) bit in UCFG1 and the RPE1 (Reset Pin Enable 1) bit in UCFG2.
Table 8. Reset pin modes RPE1 (UCFG2.0) RPE (UCFG1.6) 0 0 1 1 0 1 0 1
P1.5/RST mode General purpose input Reset input with pull-up Bidirectional reset input/output (open drain with pull-up) Reset output
Remark: During a power-up sequence, the RPE and RPE1 selection is overridden and this pin always functions as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this pin will function as defined by the RPE and RPE1 bits. Only a power-up reset will temporarily override the selection defined by RPE and RPE1 bits. Other sources of reset will not override the RPE and RPE1 bits. Remark: During a power cycle, VDD must fall below VPOR before power is reapplied, in order to ensure a power-on reset (see Table 11 "Static characteristics" on page 51). Remark: When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. Reset can be triggered from the following sources:
* * * * * *
External reset pin (during power-up or if user configured via UCFG1, UCGF2); Power-on detect; Brownout detect; Watchdog timer; Software reset; UART break character detect reset.
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a `0' to the corresponding bit. More than one flag bit may be set:
* During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
* For any other reset, previously set flag bits that have not been cleared will remain set.
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7.16.1 Reset vector
Following reset, the P89LPC952/954 will fetch instructions from either address 0000H or the Boot address. The Boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00H. The Boot address will be used if a UART break reset occurs, or the non-volatile Boot Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see P89LPC952/954 User's Manual). Otherwise, instructions will be fetched from address 0000H.
7.17 Timers/counters 0 and 1
The P89LPC952/954 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters. An option to automatically toggle the T0 and/or T1 pins upon timer overflow has been added. In the `Timer' function, the register is incremented every machine cycle. In the `Counter' function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once during every machine cycle. Timer 0 and Timer 1 have five operating modes (Modes 0, 1, 2, 3 and 6). Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different.
7.17.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
7.17.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
7.17.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.
7.17.4 Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.
7.17.5 Mode 6
In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.
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7.17.6 Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on.
7.18 RTC/system timer
The P89LPC952/954 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake-up or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all `0's, the counter will be reloaded again and the RTCF flag will be set. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as its clock source. Only power-on reset will reset the RTC and its associated SFRs to the default state.
7.19 UARTs
The P89LPC952/954 has two enhanced UARTs that are compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC952/954 does include an independent Baud Rate Generator for each UART (BRG0 for UART 0 and BRG1 for UART 1). The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator associated with the specific UART. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UARTs can be operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
7.19.1 Mode 0
Serial data enters and exits through RXDn. TXDn outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 116 of the CPU clock frequency.
7.19.2 Mode 1
10 bits are transmitted (through TXDn) or received (through RXDn): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8_n in Special Function Register SnCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 7.19.5 "Baud rate generator and selection").
7.19.3 Mode 2
11 bits are transmitted (through TXDn) or received (through RXDn): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9th data bit (TB8_n in SnCON) can be assigned the value of `0' or `1'. Or, for example, the parity bit (P, in the PSW) could be moved into TB8_n. When data is received, the 9th data bit goes into RB8_n in Special Function Register SnCON, while the
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stop bit is not saved. The baud rate is programmable to either 116 or 132 of the CPU clock frequency, as determined by the SMOD1 bit in PCON. The SMOD1 bit controls the Timer 1 output rate available to both UARTs.
7.19.4 Mode 3
11 bits are transmitted (through TXDn) or received (through RXDn): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 7.19.5 "Baud rate generator and selection").
7.19.5 Baud rate generator and selection
Each enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1_n and BRGR0_n SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UARTs can use either Timer 1 or their respective baud rate generator output (see Figure 8). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent Baud Rate Generators use OSCCLK.
timer 1 overflow (PCLK-based) /2
SMOD1 = 1
SBRGS = 0 baud rate modes 1 and 3
SMOD1 = 0 baud rate generator (CCLK-based)
SBRGS = 1
002aaa897
Fig 8.
Baud rate sources for UART (Modes 1, 3)
7.19.6 Framing error
Framing error is reported in the status register (SnSTAT). In addition, if SMOD0 (PCON.6) is `1', framing errors can be made available in SnCON.7 respectively. If SMOD0 is `0', SnCON.7 is SM0_n. It is recommended that SM0_n and SM1_n (SnCON.7:6) are set up when SMOD0 is `0'.
7.19.7 Break detect
Break detect is reported in the status register (SnSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode.
7.19.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be written to SnBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character.
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Double buffering can be disabled. If disabled (DBMOD_n, i.e., SnSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SnBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD_n = 0).
7.19.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TI_n interrupt is generated when the double buffer is ready to receive new data.
7.19.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8_n can be written before or after SnBUF is written, as long as TB8_n is updated some time before that bit is shifted out. TB8_n must not be changed until the bit is shifted out, as indicated by the TI_n interrupt. If double buffering is enabled, TB8_n must be updated before SnBUF is written, as TB8_n will be double-buffered together with SnBUF data.
7.20 I2C-bus serial interface
I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features:
* Bidirectional data transfer between masters and slaves * Multi master bus (no central master) * Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
* Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
* Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
* The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus configuration is shown in Figure 9. The P89LPC952/954 device provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
RPU
RPU
SDA I2C-bus SCL P1.3/SDA P1.2/SCL I2C MCU OTHER DEVICE WITH I2C-BUS INTERFACE OTHER DEVICE WITH I2C-BUS INTERFACE
002aab410
Fig 9.
I2C-bus configuration
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8
ADDRESS REGISTER P1.3
I2ADR
COMPARATOR INPUT FILTER P1.3/SDA OUTPUT STAGE SHIFT REGISTER ACK I2DAT 8
CCLK TIMING AND CONTROL LOGIC interrupt
INPUT FILTER P1.2/SCL OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL
SERIAL CLOCK GENERATOR
CONTROL REGISTERS AND SCL DUTY CYCLE REGISTERS 8
status bus
STATUS DECODER
I2STAT
STATUS REGISTER
8
002aaa899
Fig 10. I2C-bus serial interface block diagram
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7.21 SPI
The P89LPC952/954 provides another high-speed serial communication interface -- the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either Master or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection.
S M CPU clock 8-BIT SHIFT REGISTER DIVIDER BY 4, 16, 64, 128 READ DATA BUFFER M S PIN CONTROL LOGIC
MISO P2.3 MOSI P2.2 SPICLK P2.5 SS P2.4 SPEN
002aaa900
(c) NXP B.V. 2008. All rights reserved.
SPI clock (master) SELECT SPR1 SPR0
clock CLOCK LOGIC S M MSTR DORD MSTR CPHA SPEN CPOL SPR1 SPI CONTROL REGISTER internal data bus
SPI CONTROL WCOL SPIF
MSTR SPEN SPR0 SSIG SPI interrupt request
SPI STATUS REGISTER
Fig 11. SPI block diagram
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
* SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e., SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
* SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown in Figure 12 through Figure 14.
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7.21.1 Typical SPI configurations
master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR PORT
SPICLK SS
002aaa901
Fig 12. SPI single master single slave configuration
master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR SS
SPICLK SS SPI CLOCK GENERATOR
002aaa902
Fig 13. SPI dual device configuration, where either can be a master or a slave
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master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR port
SPICLK SS
slave MISO MOSI 8-BIT SHIFT REGISTER
SPICLK port SS
002aaa903
Fig 14. SPI single master multiple slaves configuration
7.22 Analog comparators
Two analog comparators are provided on the P89LPC952/954. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes. The overall connections to both comparators are shown in Figure 15. The comparators function to VDD = 2.4 V. When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 s. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.
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CP1 (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF Vref(bg) CN1 change detect CMF1 comparator 1 CO1 OE1
CMP1 (P0.6)
interrupt change detect CP2 CMF2 (P0.2) CIN2A (P0.1) CIN2B CMP2 (P0.0) CO2 OE2 CN2
002aaa904
EC
comparator 2
Fig 15. Comparator input and output connections
7.22.1 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as Vref(bg), is 1.23 V 10 %.
7.22.2 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt.
7.22.3 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode. If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode.
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8-bit microcontroller with 10-bit ADC
7.23 KBI
The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison. In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs.
7.24 Watchdog timer
The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 16 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few s to a few seconds. Please refer to the P89LPC952/954 User's Manual for more details.
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8-bit microcontroller with 10-bit ADC
WDL (C1H)
MOV WFEED1, #0A5H MOV WFEED2, #05AH watchdog oscillator PCLK
/32
PRESCALER
8-BIT DOWN COUNTER
reset(1)
SHADOW REGISTER
WDCON (A7H)
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
002aaa905
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence.
Fig 16. Watchdog timer in Watchdog mode (WDTE = 1)
7.25 Additional features
7.25.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.
7.25.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.
7.25.3 Debugger interface
This device contains a two-wire serial debugger interface designed to be used with commercially available debugging tools. An additional trigger output is provided that maybe triggered using the two-wire debugger interface. The Freeze register allows the user to selectively disable clocking of peripheral device timers while in the debugger mode. The two-wire serial debugger interface can also be used be used to program the code memory of these devices.
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.26 Flash program memory
7.26.1 General description
The P89LPC952/954 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP and byte-erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC952/954 flash reliably stores memory contents even after 400,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC952/954 uses VDD as the supply voltage to perform the Program/Erase algorithms.
7.26.2 Features
* * * * *
Programming and erase over the full operating voltage range. Byte erase allows code memory to be used for data storage. Read/Programming/Erase using ISP, IAP, ICP, or two-wire serial debugger. Internal fixed boot ROM, containing low-level IAP routines available to user code. Default loader providing ISP via the serial port, located in upper end of user program memory. memory space, providing flexibility to the user.
* Boot vector allows user-provided flash loader code to reside anywhere in the flash * * * * *
Any flash program/erase operation in 2 ms. Programming with industry-standard commercial programmers. Programmable security for the code in the flash for each sector. 400,000 typical erase/program cycles for each byte. 20 year minimum data retention.
7.26.3 Flash organization
The program memory consists of eight/sixteen 1 kB sectors on the P89LPC952/954 devices. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.
7.26.4 Using flash as data storage
The flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.
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7.26.5 Flash programming and erasing
Four different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IAP) under control of the application's firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock/serial data interface. As shipped from the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing for the device to be programmed in circuit through the serial port. The flash may also be programmed or erased using a commercially available EPROM programmer which supports this device. This device does not provide for direct verification of code memory contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire user code space.
7.26.6 ICP
ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC952/954 through a two-wire serial interface. The Philips ICP facility has made in-circuit programming in an embedded application--using commercially available programmers--possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC952/954 User's Manual.
7.26.7 IAP
IAP is performed in the application under the control of the microcontroller's firmware. The IAP facility consists of internal hardware resources to facilitate programming and erasing. The Philips IAP has made in-application programming in an embedded application possible without additional components. Two methods are available to accomplish IAP. A set of predefined IAP functions are provided in a Boot ROM and can be called through a common interface, PGM_MTP. Several IAP calls are available for use by an application program to permit selective erasing and programming of flash sectors, pages, security bits, configuration bytes, and device ID. These functions are selected by setting up the microcontroller's registers before making a call to PGM_MTP at FF03H. The Boot ROM occupies the program memory space at the top of the address space from FF00H to FEFFH, thereby not conflicting with the user program memory space. In addition, IAP operations can be accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC952/954 User's Manual.
7.26.8 ISP
ISP is performed without removing the microcontroller from the system. The ISP facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC952/954 through the serial port. This firmware is provided by Philips and embedded within each P89LPC952/954 device. The Philips ISP facility has made in-system programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins (VDD, VSS, TXD, RXD, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature.
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7.26.9 Power-on reset code execution
The P89LPC952/954 contains two special flash elements: the Boot Vector and the Boot Status bit. Following reset, the P89LPC952/954 examines the contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user's application code. When the Boot Status bit is set to a value other than zero, the contents of the Boot Vector are used as the high byte of the execution address and the low byte is set to 00H. Table 9 shows the factory default Boot Vector setting for these devices. A factory-provided bootloader is pre-programmed into the address space indicated and uses the indicated bootloader entry point to perform ISP functions. This code can be erased by the user. Users who wish to use this loader should take precautions to avoid erasing the 1 kB sector that contains this bootloader. Instead, the page erase function can be used to erase the first eight 64-byte pages located in this sector. A custom bootloader can be written with the Boot Vector set to the custom bootloader, if desired.
Table 9. Device Default boot vector values and ISP entry points Default boot vector 1FH 3FH Default bootloader entry point 1F00H 3F00H Default bootloader 1 kB sector code range range 1E00H to 1FFFH 3E00H to 3FFFH 1C00H to 1FFFH 3C00H to 3FFFH
P89LPC952 P89LPC954
7.26.10 Hardware activation of the bootloader
The bootloader can also be executed by forcing the device into ISP mode during a power-on sequence (see the P89LPC952/954 User's Manual for specific information). This has the same effect as having a non-zero status byte. This allows an application to be built that will normally execute user code but can be manually forced into ISP operation. If the factory default setting for the boot vector (1FH/3FH) is changed, it will no longer point to the factory pre-programmed ISP bootloader code. After programming the flash, the status byte should be programmed to zero in order to allow execution of the user's application code beginning at address 0000H.
7.27 User configuration bytes
Some user-configurable features of the P89LPC952/954 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the flash byte UCFG1. Please see the P89LPC952/954 User's Manual for additional details.
7.28 User sector security bytes
There are eight/sixteen User Sector Security Bytes on the P89LPC952/954. Each byte corresponds to one sector. Please see the P89LPC952/954 User's Manual for additional details.
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8-bit microcontroller with 10-bit ADC
8. ADC
8.1 General description
The P89LPC952/954 has a 10-bit, 8-channel multiplexed successive approximation ADC module. A block diagram of the ADC is shown in Figure 17. The ADC consists of an 8-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the SAR drives a DAC which provides the other input to the comparator. The output of the comparator is fed to the SAR.
8.2 Features
I 10-bit, 8-channel multiplexed input, successive approximation ADC. I Eight result register pairs. I Six operating modes: N Fixed channel, single conversion mode. N Fixed channel, continuous conversion mode. N Auto scan, single conversion mode. N Auto scan, continuous conversion mode. N Dual channel, continuous conversion mode. N Single step mode. I Three conversion start modes: N Timer triggered start. N Start immediately. N Edge triggered. I 10-bit conversion time of 4 s at an A/D clock of 9 MHz. I Interrupt or polled operation. I High and low boundary limits interrupt; selectable in or out-of-range. I Clock divider. I Power-down mode.
8.3 Block diagram
comp + INPUT MUX SAR - CONTROL LOGIC DAC0 8
CCLK
002aab103
Fig 17. ADC block diagram
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8.4 ADC operating modes
8.4.1 Fixed channel, single conversion mode
A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register pair which corresponds to the selected input channel. An interrupt, if enabled, will be generated after the conversion completes.
8.4.2 Fixed channel, continuous conversion mode
A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the eight result register pairs. The user may select whether an interrupt can be generated after every four or every eight conversions. Additional conversion results will again cycle through the result register pairs, overwriting the previous results. Continuous conversions continue until terminated by the user.
8.4.3 Auto scan, single conversion mode
Any combination of the eight input channels can be selected for conversion. A single conversion of each selected input will be performed and the result placed in the result register pair which corresponds to the selected input channel. The user may select whether an interrupt, if enabled, will be generated after either the first four conversions have occurred or all selected channels have been converted. If the user selects to generate an interrupt after the four input channels have been converted, a second interrupt will be generated after the remaining input channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode.
8.4.4 Auto scan, continuous conversion mode
Any combination of the eight input channels can be selected for conversion. A conversion of each selected input will be performed and the result placed in the result register pair which corresponds to the selected input channel. The user may select whether an interrupt, if enabled, will be generated after either the first four conversions have occurred or all selected channels have been converted. If the user selects to generate an interrupt after the four input channels have been converted, a second interrupt will be generated after the remaining input channels have been converted. After all selected channels have been converted, the process will repeat starting with the first selected channel. Additional conversion results will again cycle through the eight result register pairs, overwriting the previous results. Continuous conversions continue until terminated by the user.
8.4.5 Dual channel, continuous conversion mode
This is a variation of the auto scan continuous conversion mode where conversion occurs on two user-selectable inputs. The result of the conversion of the first channel is placed in the result register pair, AD0DAT0R and AD0DAT0L. The result of the conversion of the second channel is placed in result register pair, AD0DAT1R and AD0DAT1L. The first channel is again converted and its result stored in AD0DAT2R and AD0DAT2L. The second channel is again converted and its result placed in AD0DAT3R and AD0DAT3L, etc. An interrupt is generated, if enabled, after every set of four or eight conversions (user selectable).
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8.4.6 Single step mode
This special mode allows `single-stepping' in an auto scan conversion mode. Any combination of the eight input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the ADC waits for the next start condition. May be used with any of the start modes.
8.5 Conversion start modes
8.5.1 Timer triggered start
An A/D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all ADC operating modes.
8.5.2 Start immediately
Programming this mode immediately starts a conversion. This start mode is available in all ADC operating modes.
8.5.3 Edge triggered
An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until the conversion has completed. The edge triggered start mode is available in all ADC operating modes.
8.6 Boundary limits interrupt
The ADC has both a high and low boundary limit register. The user may select whether an interrupt is generated when the conversion result is within (or equal to) the high and low boundary limits or when the conversion result is outside the boundary limits. An interrupt will be generated, if enabled, if the result meets the selected interrupt criteria. The boundary limit may be disabled by clearing the boundary limit interrupt enable. An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits. In this case, after the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary high and low registers. If the four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits) an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt criteria, the boundary limits will again be compared after all 8 MSBs have been converted. A boundary status register (BNDSTA0) flags the channels which caused a boundary interrupt.
8.7 Clock divider
The ADC requires that its internal clock source be in the range of 320 kHz to 9 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose.
8.8 Power-down and Idle mode
In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the ADC does not function. If the ADC is enabled, it will consume power. Power can be reduced by disabling the ADC.
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9. Limiting values
Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Tamb(bias) Tstg IOH(I/O) IOL(I/O) II/Otot(max) Vn Ptot(pack) Parameter bias ambient temperature storage temperature HIGH-level output current per input/output pin LOW-level output current per input/output pin maximum total input/output current voltage on any other pin total power dissipation (per package) except VSS, with respect to VDD based on package heat transfer, not device power consumption Conditions Min -55 -65 Max +125 +150 20 20 100 3.5 1.5 Unit C C mA mA mA V W
[1]
The following applies to Table 10: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
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10. Static characteristics
Table 11. Static characteristics VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol IDD(oper) Parameter operating supply current Conditions VDD = 3.6 V; fosc = 12 MHz VDD = 3.6 V; fosc = 18 MHz IDD(idle) Idle mode supply current VDD = 3.6 V; fosc = 12 MHz VDD = 3.6 V; fosc = 18 MHz IDD(pd) Power-down mode supply current total Power-down mode supply current rise rate fall rate power-on reset voltage data retention supply voltage HIGH-LOW threshold voltage LOW-level input voltage LOW-HIGH threshold voltage HIGH-level input voltage hysteresis voltage LOW-level output voltage except SCL, SDA SCL, SDA only except SCL, SDA SCL, SDA only port 1 IOL = 20 mA; VDD = 2.4 V to 3.6 V all ports, all modes except high-Z IOL = 3.2 mA; VDD = 2.4 V to 3.6 V all ports, all modes except high-Z VOH HIGH-level output voltage IOH = -20 A; VDD = 2.4 V to 3.6 V; all ports, quasi-bidirectional mode IOH = -3.2 mA; VDD = 2.4 V to 3.6 V; all ports, push-pull mode IOH = -20 mA; VDD = 2.4 V to 3.6 V; Port 5, push-pull mode Vxtal Vn crystal voltage voltage on any other pin on XTAL1, XTAL2 pins; with respect to VSS except XTAL1, XTAL2, VDD; with respect to VSS
[5] [4] [2]
Min -
Typ[1] 11 14 3.25 5 55
Max 18 23 5 7 80
Unit mA mA mA mA A
[2]
[2]
[2]
VDD = 3.6 V; voltage comparators powered down VDD = 3.6 V of VDD of VDD
[2]
IDD(tpd) (dV/dt)r (dV/dt)f VPOR VDDR Vth(HL) VIL Vth(LH) VIH Vhys VOL
[3]
1.5 0.22VDD -0.5 0.7VDD -
0.5 0.4VDD 0.6VDD 0.2VDD 0.6
5 2 50 0.5 0.3VDD 0.7VDD 5.5 1.0
A mV/s mV/s V V V V V V V V
[4]
-
0.2
0.3
V
VDD - 0.3
VDD - 0. 2
V
VDD - 0.7
VDD - 0. 4 -
V
0.8VDD
V
-0.5 -0.5
-
+4.0 +5.5
V V
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Table 11. Static characteristics ...continued VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol Ciss IIL ILI ITHL Parameter input capacitance LOW-level input current input leakage current HIGH-LOW transition current VI = 0.4 V VI = VIL, VIH, or Vth(HL) all ports; VI = 1.5 V at VDD = 3.6 V pin RST BOE = 1 Conditions
[6] [7] [8] [9]
Min -30 10 2.4 1.19 -
Typ[1] 1.23 10
Max 15 -80 1 -450 30 2.7 1.27 20
Unit pF A A A k V V ppm/C
RRST_N(int) internal pull-up resistance on pin RST Vbo Vref(bg) TCbg brownout trip voltage band gap reference voltage band gap temperature coefficient
[1] [2] [3] [4] [5]
Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. The IDD(oper), IDD(idle), and IDD(pd) specifications are measured using an external clock with the following functions disabled: comparators, real-time clock, and watchdog timer. The IDD(tpd) specification is measured using an external clock with the following functions disabled: comparators, real-time clock, brownout detect, and watchdog timer. See Section 9 "Limiting values" for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition, VOL/VOH may exceed the related specification. This specification can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used for those analog functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with respect to VSS. Pin capacitance is characterized but not tested. Measured with port in quasi-bidirectional mode. Measured with port in high-impedance mode. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when VI is approximately 2 V.
[6] [7] [8] [9]
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11. Dynamic characteristics
Table 12. Dynamic characteristics (12 MHz) VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified.[1][2] Symbol fosc(RC) Parameter internal RC oscillator frequency Conditions nominal f = 7.3728 MHz trimmed to 1 % at Tamb = 25 C; clock doubler option = OFF (default) nominal f = 14.7456 MHz; clock doubler option = ON, VDD = 2.7 V to 3.6 V fosc(WD) fosc Tcy(clk) fCLKLP Glitch filter tgr tsa glitch rejection time signal acceptance time P1.5/RST pin any pin except P1.5/RST P1.5/RST pin any pin except P1.5/RST External clock tCHCX tCLCX tCLCH tCHCL TXLXL tQVXH tXHQX tXHDX tXHDV clock HIGH time clock LOW time clock rise time clock fall time serial port clock cycle time output data set-up to clock rising edge time output data hold after clock rising edge time input data hold after clock rising edge time input data valid to clock rising edge time SPI operating frequency slave master 0 CCLK 6 CCLK 4
Variable clock Min 7.189 Max 7.557
fosc = 12 MHz Min 7.189 Max
Unit
7.557 MHz
14.378
15.114
14.378 15.114 MHz
internal watchdog oscillator frequency oscillator frequency clock cycle time low-power select clock frequency see Figure 19
320 0 83 0
520 12 8
320 -
520 -
kHz MHz ns MHz
125 50 33 33 16Tcy(clk) 13Tcy(clk) 150
50 15 Tcy(clk) - tCLCX Tcy(clk) - tCHCX 8 8 Tcy(clk) + 20 0 -
125 50 33 33 1333 1083 150
50 15 8 8 103 0 -
ns ns ns ns ns ns ns ns ns ns ns ns ns
see Figure 19 see Figure 19 see Figure 19 see Figure 19 see Figure 18 see Figure 18 see Figure 18 see Figure 18 see Figure 18
Shift register (UART mode 0)
SPI interface fSPI 0 2.0 3.0 MHz MHz
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Table 12. Dynamic characteristics (12 MHz) ...continued VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified.[1][2] Symbol TSPICYC Parameter SPI cycle time slave master tSPILEAD tSPILAG tSPICLKH SPI enable lead time slave SPI enable lag time slave SPICLK HIGH time master slave tSPICLKL SPICLK LOW time master slave tSPIDSU tSPIDH tSPIA tSPIDIS tSPIDV SPI data set-up time master or slave SPI data hold time master or slave SPI access time slave SPI disable time slave SPI enable to output data valid time slave master tSPIOH tSPIR SPI output data hold time SPI rise time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) tSPIF SPI fall time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS)
[1] [2]
Conditions see Figure 20, 21, 22, 23
Variable clock Min
6 CCLK 4 CCLK
fosc = 12 MHz Min 500 333 250 250 165 250 165 250 100 100 0 Max 120 240
Unit
Max 120 240
ns ns ns ns ns ns ns ns ns ns ns ns
see Figure 22, 23 250 see Figure 22, 23 250 see Figure 20, 21, 22, 23
2 CCLK 3 CCLK
see Figure 20, 21, 22, 23
2 CCLK 3 CCLK
see Figure 20, 21, 22, 23 100 see Figure 20, 21, 22, 23 100 see Figure 22, 23 0 see Figure 22, 23 0 see Figure 20, 21, 22, 23 see Figure 20, 21, 22, 23 see Figure 20, 21, 22, 23 see Figure 20, 21, 22, 23 100 2000 100 2000 ns ns 100 2000 100 2000 ns ns 0 240 167 0 240 167 ns ns ns
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
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8-bit microcontroller with 10-bit ADC
Table 13. Dynamic characteristics (18 MHz) VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified.[1][2] Symbol fosc(RC) Parameter internal RC oscillator frequency Conditions nominal f = 7.3728 MHz trimmed to 1 % at Tamb = 25 C; clock doubler option = OFF (default) nominal f = 14.7456 MHz; clock doubler option = ON fosc(WD) fosc Tcy(clk) fCLKLP internal watchdog oscillator frequency oscillator frequency clock cycle time low-power select clock frequency glitch rejection time signal acceptance time P1.5/RST pin any pin except P1.5/RST tsa P1.5/RST pin any pin except P1.5/RST External clock tCHCX tCLCX tCLCH tCHCL TXLXL tQVXH tXHQX tXHDX tXHDV clock HIGH time clock LOW time clock rise time clock fall time serial port clock cycle time output data set-up to clock rising edge time output data hold after clock rising edge time input data hold after clock rising edge time input data valid to clock rising edge time SPI operating frequency slave master TSPICYC SPI cycle time slave master see Figure 20, 21, 22, 23
6 CCLK 4 CCLK
Variable clock Min 7.189 Max 7.557
fosc = 18 MHz Min 7.189 Max
Unit
7.557 MHz
14.378 320 0
15.114 520 18 8
14.378 15.114 MHz 320 520 kHz MHz ns MHz
see Figure 19
55 0
Glitch filter tgr 125 50 22 22 16Tcy(clk) 13Tcy(clk) 150 50 15 Tcy(clk) - tCLCX Tcy(clk) - tCHCX 5 5 Tcy(clk) + 20 0 125 50 22 22 888 722 150 50 15 5 5 75 0 ns ns ns ns ns ns ns ns ns ns ns ns ns
see Figure 19 see Figure 19 see Figure 19 see Figure 19 see Figure 18 see Figure 18 see Figure 18 see Figure 18 see Figure 18
Shift register (UART mode 0)
SPI interface fSPI 0 CCLK CCLK
6 4
0 333 222
3.0 4.5 -
MHz MHz ns ns
-
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8-bit microcontroller with 10-bit ADC
Table 13. Dynamic characteristics (18 MHz) ...continued VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified.[1][2] Symbol tSPILEAD tSPILAG tSPICLKH Parameter SPI enable lead time slave SPI enable lag time slave SPICLK HIGH time slave master tSPICLKL SPICLK LOW time slave master tSPIDSU tSPIDH tSPIA tSPIDIS tSPIDV SPI data set-up time master or slave SPI data hold time master or slave SPI access time slave SPI disable time slave SPI enable to output data valid time slave master tSPIOH tSPIR SPI output data hold time SPI rise time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) tSPIF SPI fall time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS)
[1] [2]
Conditions see Figure 22, 23
Variable clock Min 250 Max 80 160
fosc = 18 MHz Min 250 250 167 111 167 111 100 100 0 Max 80 160
Unit
ns ns ns ns ns ns ns ns ns ns
see Figure 22, 23 250 see Figure 20, 21, 22, 23
3 CCLK 2 CCLK
see Figure 20, 21, 22, 23
3 CCLK 2 CCLK
see Figure 20, 21, 22, 23 100 see Figure 20, 21, 22, 23 100 see Figure 22, 23 0 see Figure 22, 23 0 see Figure 20, 21, 22, 23 see Figure 20, 21, 22, 23 see Figure 20, 21, 22, 23 see Figure 20, 21, 22, 23 100 2000 100 2000 ns ns 100 2000 100 2000 ns ns 0 160 111 0 160 111 ns ns ns
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
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8-bit microcontroller with 10-bit ADC
11.1 Waveforms
TXLXL clock tQVXH output data 0 write to SBUF input data clear RI set RI
002aaa906
tXHQX 1 tXHDX 2 3 4 5 6 7
tXHDV
valid valid valid valid valid valid valid
set TI
valid
Fig 18. Shift register mode timing
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
Fig 19. External clock timing
SS TSPICYC tSPIF tSPICLKH SPICLK (CPOL = 0) (output) tSPIF tSPICLKL tSPIR tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH LSB/MSB in tSPIOH tSPIDV tSPIR tSPICLKL tSPIR
MSB/LSB in tSPIDV
MOSI (output)
tSPIF master MSB/LSB out master LSB/MSB out
002aaa908
Fig 20. SPI master timing (CPHA = 0)
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8-bit microcontroller with 10-bit ADC
SS TSPICYC tSPIF tSPICLKL tSPIR tSPICLKH
SPICLK (CPOL = 0) (output) tSPIF SPICLK (CPOL = 1) (output) tSPICLKH tSPICLKL tSPIR
tSPIDSU MISO (input)
tSPIDH LSB/MSB in tSPIOH tSPIDV tSPIDV tSPIR
MSB/LSB in tSPIDV
MOSI (output)
tSPIF master MSB/LSB out master LSB/MSB out
002aaa909
Fig 21. SPI master timing (CPHA = 1)
SS
tSPIR tSPILEAD SPICLK (CPOL = 0) (input) tSPIF SPICLK (CPOL = 1) (input) tSPIA tSPIOH tSPIDV MISO (output) tSPIF
TSPICYC tSPICLKH tSPICLKL tSPIR tSPILAG
tSPIR
tSPICLKL
tSPIR tSPICLKH
tSPIOH tSPIDV
tSPIOH
tSPIDIS
slave MSB/LSB out
slave LSB/MSB out
not defined
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDSU
tSPIDH
MSB/LSB in
LSB/MSB in
002aaa910
Fig 22. SPI slave timing (CPHA = 0)
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
SS tSPIR tSPILEAD SPICLK (CPOL = 0) (input) tSPIF SPICLK (CPOL = 1) (input) tSPIOH tSPIDV tSPIA MISO (output) not defined slave MSB/LSB out slave LSB/MSB out tSPICLKL tSPIR tSPICLKH tSPIF tSPICLKH tSPIR tSPIR tSPILAG
TSPICYC tSPICLKL
tSPIOH tSPIDV
tSPIOH tSPIDV tSPIDIS
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDSU
tSPIDH
MSB/LSB in
LSB/MSB in
002aaa911
Fig 23. SPI slave timing (CPHA = 1)
11.2 ISP entry mode
Table 14. Dynamic characteristics, ISP entry mode VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol tVR tRH tRL Parameter RST HIGH time RST LOW time Conditions pin RST pin RST Min 50 1 1 Typ Max 32 Unit s s s VDD active to RST active delay time pin RST
VDD tVR RST tRL
002aaa912
tRH
Fig 24. ISP entry waveform
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8-bit microcontroller with 10-bit ADC
12. Other characteristics
12.1 Comparator electrical characteristics
Table 15. Comparator electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol VIO VIC CMRR tres(tot) t(CE-OV) ILI
[1]
Parameter input offset voltage common-mode input voltage common-mode rejection ratio total response time chip enable to output valid time input leakage current
Conditions
Min 0
[1]
Typ 250 -
Max 10 VDD - 0.3 -50 500 10 10
Unit mV V dB ns s A
-
0 V < VI < VDD
-
This parameter is characterized, but not tested in production.
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8-bit microcontroller with 10-bit ADC
12.2 ADC electrical characteristics
Table 16. ADC electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. All limits valid for an external source impedance of less than 10 k. Symbol VDDA(ADC) VSSA VVREFP VVREFN VIA Cia ED EL(adj) EO EG Eu(tot) MCTC ct(port) SRin Tcy(ADC) tADC Parameter ADC analog supply voltage analog ground voltage voltage on pin VREFP voltage on pin VREFN analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error total unadjusted error channel-to-channel matching crosstalk between port inputs input slew rate ADC clock cycle time ADC conversion time ADC enabled 0 kHz to 100 kHz Conditions Min Typ Max VDD + 0.4 VSS + 0.4 VDD + 0.4 VSS + 0.4 VDD + 0.4 15 1 2 2 2 +4/-3 1 -60 100 3125 36Tcy(ADC) Unit V V V V V pF LSB LSB LSB LSB LSB LSB dB V/ms ns s VDD - 0.4 VSS - 0.4 VDD - 0.4 VSS - 0.4 VSS - 0.4 111 -
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8-bit microcontroller with 10-bit ADC
13. Package outline
PLCC44: plastic leaded chip carrier; 44 leads SOT187-2
eD y X A ZE
eE
39
29 28
bp
40
b1 wM 44 HE A e A4 A1 (A 3) k 7 e D HD 17 ZD B vMB vM A 6 18 Lp detail X
1
pin 1 index
E
0
5 scale
10 mm
DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 e UNIT A A3 D(1) E(1) eD eE HD bp b1 max. min.
mm inches 4.57 4.19 0.51 0.25 0.01 3.05 0.12 0.53 0.33 0.81 0.66
HE
k
Lp
1.44 1.02
v
0.18
w
0.18
y
0.1
ZD(1) ZE(1) max. max.
2.16 2.16
16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.63 0.59 0.63 0.59
45 o
0.180 0.02 0.165
0.021 0.032 0.656 0.656 0.05 0.013 0.026 0.650 0.650
0.695 0.695 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.685 0.685 0.042 0.040
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT187-2 REFERENCES IEC 112E10 JEDEC MS-018 JEITA EDR-7319 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 01-11-14
Fig 25. Package outline SOT187-2 (PLCC44)
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8-bit microcontroller with 10-bit ADC
LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm
SOT389-1
c
y X
A 33 34 23 22 ZE
e E HE wM bp 44 1 bp D HD wM 11 ZD B vM B vM A 12 detail X L Lp A A2 A1 pin 1 index (A 3)
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.45 0.30 c 0.20 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.14 0.85 1.14 0.85 7 o 0
o
12.15 12.15 11.85 11.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT389-1 REFERENCES IEC 136E08 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 02-06-07
Fig 26. Package outline SOT389-1 (LQFP44)
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Product data sheet
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 27. Package outline SOT313-2 (LQFP48)
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Product data sheet
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
14. Abbreviations
Table 17. Acronym ADC BOE CPU CCU CRC DAC EPROM EMI IAP LSB MSB PWM RAM RC RTC SAR SFR SPI UART Abbreviations Description Analog-to-Digital Converter BrownOut Enable Central Processing Unit Capture/Compare Unit Cyclic Redundancy Check Digital-to-Analog Converter Erasable Programmable Read-Only Memory ElectroMagnetic Interference In-Application Programming Least Significant Bit Most Significant Bit Pulse Width Modulator Random Access Memory Resistance-Capacitance Real-Time Clock Successive Approximation Register Special Function Register Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter
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8-bit microcontroller with 10-bit ADC
15. Revision history
Table 18. Revision history Release date 20080724 Data sheet status Product data sheet Product data sheet Preliminary data sheet Preliminary data sheet Change notice Supersedes P89LPC952_954_3 P89LPC952_954_2 P89LPC952_1 Document ID P89LPC952_954_4 Modifications: P89LPC952_954_3 P89LPC952_954_2 P89LPC952_1
*
Figure 2 "Functional diagram": Updated port 2 information.
20080605 20071219 20050916
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P89LPC952/954
8-bit microcontroller with 10-bit ADC
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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8-bit microcontroller with 10-bit ADC
18. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Functional description . . . . . . . . . . . . . . . . . . 14 7.1 Special function registers . . . . . . . . . . . . . . . . 14 7.2 Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3.1 Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 23 7.3.2 CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 23 7.3.3 Low speed oscillator option . . . . . . . . . . . . . . 23 7.3.4 Medium speed oscillator option . . . . . . . . . . . 23 7.3.5 High speed oscillator option . . . . . . . . . . . . . . 23 7.3.6 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.4 On-chip RC oscillator option . . . . . . . . . . . . . . 24 7.5 Watchdog oscillator option . . . . . . . . . . . . . . . 24 7.6 External clock input option . . . . . . . . . . . . . . . 24 7.7 CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 25 7.8 CCLK modification: DIVM register . . . . . . . . . 25 7.9 Low power select . . . . . . . . . . . . . . . . . . . . . . 25 7.10 Memory organization . . . . . . . . . . . . . . . . . . . 26 7.11 Data RAM arrangement . . . . . . . . . . . . . . . . . 26 7.12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.12.1 External interrupt inputs . . . . . . . . . . . . . . . . . 27 7.13 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.13.1 Port configurations . . . . . . . . . . . . . . . . . . . . . 29 7.13.1.1 Quasi-bidirectional output configuration . . . . . 29 7.13.1.2 Open-drain output configuration . . . . . . . . . . . 29 7.13.1.3 Input-only configuration . . . . . . . . . . . . . . . . . 30 7.13.1.4 Push-pull output configuration . . . . . . . . . . . . 30 7.13.2 Port 0 analog functions . . . . . . . . . . . . . . . . . . 30 7.13.3 Additional port features. . . . . . . . . . . . . . . . . . 30 7.14 Power monitoring functions. . . . . . . . . . . . . . . 30 7.14.1 Brownout detection . . . . . . . . . . . . . . . . . . . . . 30 7.14.2 Power-on detection . . . . . . . . . . . . . . . . . . . . . 31 7.15 Power reduction modes . . . . . . . . . . . . . . . . . 31 7.15.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.15.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . 31 7.15.3 Total Power-down mode . . . . . . . . . . . . . . . . . 31 7.16 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.16.1 7.17 7.17.1 7.17.2 7.17.3 7.17.4 7.17.5 7.17.6 7.18 7.19 7.19.1 7.19.2 7.19.3 7.19.4 7.19.5 7.19.6 7.19.7 7.19.8 7.19.9 7.19.10 7.20 7.21 7.21.1 7.22 7.22.1 7.22.2 7.22.3 7.23 7.24 7.25 7.25.1 7.25.2 7.25.3 7.26 7.26.1 7.26.2 7.26.3 7.26.4 7.26.5 7.26.6 7.26.7 7.26.8 7.26.9 7.26.10 7.27 7.28 Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . Timers/counters 0 and 1 . . . . . . . . . . . . . . . . Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer overflow toggle output . . . . . . . . . . . . . RTC/system timer. . . . . . . . . . . . . . . . . . . . . . UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud rate generator and selection . . . . . . . . . Framing error . . . . . . . . . . . . . . . . . . . . . . . . . Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . Double buffering . . . . . . . . . . . . . . . . . . . . . . . Transmit interrupts with double buffering enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . I2C-bus serial interface. . . . . . . . . . . . . . . . . . SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical SPI configurations . . . . . . . . . . . . . . . Analog comparators . . . . . . . . . . . . . . . . . . . . Internal reference voltage. . . . . . . . . . . . . . . . Comparator interrupt . . . . . . . . . . . . . . . . . . . Comparators and power reduction modes . . . KBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . Additional features . . . . . . . . . . . . . . . . . . . . . Software reset . . . . . . . . . . . . . . . . . . . . . . . . Dual data pointers . . . . . . . . . . . . . . . . . . . . . Debugger interface. . . . . . . . . . . . . . . . . . . . . Flash program memory . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash organization . . . . . . . . . . . . . . . . . . . . . Using flash as data storage . . . . . . . . . . . . . . Flash programming and erasing. . . . . . . . . . . ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on reset code execution . . . . . . . . . . . Hardware activation of the bootloader . . . . . . User configuration bytes. . . . . . . . . . . . . . . . . User sector security bytes . . . . . . . . . . . . . . . 33 33 33 33 33 33 33 34 34 34 34 34 34 35 35 35 35 35 36 36 36 38 39 40 41 41 41 42 42 43 43 43 43 44 44 44 44 44 45 45 45 45 46 46 46 46
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P89LPC952_954_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 24 July 2008
68 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
47 47 47 47 48 48 48 48 48 48 49 49 49 49 49 49 49 49 50 51 53 57 59 60 60 61 62 65 66 67 67 67 67 67 67 68
8 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.5 8.5.1 8.5.2 8.5.3 8.6 8.7 8.8 9 10 11 11.1 11.2 12 12.1 12.2 13 14 15 16 16.1 16.2 16.3 16.4 17 18
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General description. . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . ADC operating modes . . . . . . . . . . . . . . . . . . Fixed channel, single conversion mode . . . . . Fixed channel, continuous conversion mode . Auto scan, single conversion mode . . . . . . . . Auto scan, continuous conversion mode . . . . Dual channel, continuous conversion mode . . Single step mode . . . . . . . . . . . . . . . . . . . . . . Conversion start modes . . . . . . . . . . . . . . . . . Timer triggered start . . . . . . . . . . . . . . . . . . . . Start immediately . . . . . . . . . . . . . . . . . . . . . . Edge triggered . . . . . . . . . . . . . . . . . . . . . . . . Boundary limits interrupt. . . . . . . . . . . . . . . . . Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . Power-down and Idle mode . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics. . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . . Other characteristics . . . . . . . . . . . . . . . . . . . . Comparator electrical characteristics . . . . . . . ADC electrical characteristics . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 July 2008 Document identifier: P89LPC952_954_4

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